Wireless communication devices have become smaller and more powerful as well as more capable. Increasingly users rely on wireless communication devices for mobile phone use as well as email and Internet access. At the same time, devices have become smaller in size. Devices such as cellular telephones, personal digital assistants (PDAs), laptop computers, and other similar devices provide reliable service with expanded coverage areas. Such devices may be referred to as mobile stations, stations, access terminals, user terminals, subscriber units, user equipment, and similar terms. Other electronic devices such as tablet computers and gaming devices incorporate chipsets to provide a wide variety of functions. These devices rely on increasingly complex chipsets that require complex and thorough testing before installation into an end device.
As electronic devices have grown in use and popularity, they have also increased in complexity. Most electronic devices rely on one or more chipsets to provide increasing levels of functionality. Users rely heavily on these devices and it is critical that the devices perform as promised. This requires that the chipsets incorporated into the devices be thoroughly tested and evaluated for various defects before incorporation into an end product. During testing, some devices may exhibit performance limitations (including minimum operating voltage and maximum operating frequency). These are called “soft failures”. Devices exhibiting “soft failures” may undergo failure analysis in order to determine the root cause of the marginal failures. Electrical fault isolation is a fundamental failure analysis protocol which allows the failure to be narrowed down to a few failing transistors or logic cells.
Electrical fault isolation in a chipset typically involves testing an integrated circuit (IC) die. One of many fault isolation techniques is Laser Voltage Probing (LVP), which allows waveforms to be measured directly from the backside of the chip. This technique uses a laser source of a specific wavelength and aims it on a transistor source or drain region. The incoming laser source gets reflected and modulated by the switching of the active transistor, thus allowing either a frequency map of the chip or a plot of the waveform to be created.
However, in the case of soft defect failures, the laser voltage probing may inadvertently stimulate the transistor being probed and thus may cause a false pass of the circuit being tested. This may cause inaccuracy with respect to the waveforms. Hence, instead of laser voltage probing, a laser stimulation technique which provides a contour map of the minimum operating voltage (Vmin) and maximum operating frequency (Fmax) has been needed and has been developed. As part of the testing, a LVP is used to stimulate the semiconductor circuit while measuring the parameters such as Vmin and Fmax at both laser and no laser conditions. The improvement in Vmin and Fmax is recorded and plotted as a contour map across the field of view. At the present time, this process is performed manually and is time consuming and inefficient.
Thus, there is a need in the art for a method and apparatus to automate the laser positioning and contour mapping for use in diagnosing marginal voltage and frequency failures in chipsets, and aid in localizing any defects identified.